The core of electronic design technology is EDA technology. EDA refers to the electronic CAD general software package developed by computer as the working platform and the application of electronic technology, computer technology and intelligent technology. It can mainly assist in the design work of three aspects. , namely IC design, electronic circuit design and PCB design. EDA technology has been in development for 30 years and can be roughly divided into three stages. In the computer-aided design (CAD) stage in the 1970s, people began to use computer-aided IC layout editing and PCB layout to replace manual operations. The 1980s was the Computer Aided Engineering (CAE) phase. Compared with CAD, CAE adds circuit function design and structural design in addition to pure graphic drawing function, and combines the two through electrical connection network table to realize engineering design. The main functions of CAE are: schematic input, logic simulation, circuit analysis, automatic place and route, post-PCB analysis. The 1990s was the Electronic Design Automation (EDA) phase.
The basic characteristics of EDA technology EDA represents the latest development direction of today's electronic design technology. Its basic characteristics are: designers follow the "top-down" design method, the whole system is designed and functionally divided, the key circuit of the system Implemented in one or several application-specific integrated circuits (ASICs), then implemented in a hardware description language (HDL) to perform system behavioral design, and finally through the synthesizer and adapter to generate the final target device. This design method is called high-level electronics. Design method. The following are some of the concepts related to the basic features of EDA.
1. "Top-down" design approach. Ten years ago, the basic idea of ​​electronic design was to use a standard integrated circuit to construct a new system from the bottom up. This design method is like building a pyramid with the same brick and tile, which is not only inefficient, costly and error-prone.
High-level design is a new design method of “top-downâ€. This design method firstly divides the functional block diagram and structure design from the system design. Simulation and error correction are performed at the block diagram level, and high-level system behavior is described by hardware description language, and verification is performed at the system level. Then, a comprehensive optimization tool is used to generate a network table of specific gates, and the corresponding physical implementation level may be a printed circuit board or an application specific integrated circuit. Since the main simulation and debugging process of the design is completed at a high level, it is beneficial to early detection of structural design errors, waste of avoidance of fuel gauge work, reduction of workload of logic function simulation, and improvement of design once. Success rate.
2. ASIC design. The complexity of modern electronic products is increasing. An electronic system may consist of tens of thousands of small and medium-sized integrated circuits, which brings about large size, high power consumption and poor reliability. An effective way to solve this problem is to design with an ASIC chip. ASICs can be divided into fully custom ASICs, semi-custom ASCs, and ASICs (also known as programmable logic devices) depending on the design methodology.
When designing a fully custom ASIC chip, the designer has to define the geometry and process rules of all the transistors on the chip. Finally, the design result is handed over to the m manufacturer for the mold manufacturing and product making. The advantage of this design method is that the chip can obtain the optimal performance, that is, the area utilization rate is high, the speed is fast, and the power consumption is low, and the disadvantage is that the development cycle is long and the cost is high, and it is only suitable for mass product development.
The layout design method of semi-custom ASIC chips is divided into gate array design method and standard cell design method. Both methods are binding design methods. The main purpose is to simplify the design and shorten the development time at the expense of chip performance.
The difference between the programmable logic chip and the above mask ASIC is that after the designer completes the layout design, the chip can be fired in the laboratory.
The development cycle is greatly shortened without the involvement of IC manufacturers.
Programmable logic devices have experienced several development stages of PAL, GALGPLD, and FPGA since the 1970s. Among them, CPLD/FPGA high-density programmable logic devices have a current integration level of 2 million gates/chip, which will be a grid ASC integration. The combination of high-performance and programmable logic device design and production features is especially suitable for sample development or small-volume product development, so that the product can be listed at the fastest speed, and when the market expands, it can be easily transferred. Implemented by a mask ASIC, the development risk is also greatly reduced.
The above ASIC chips, especially CPLD/FPGA devices, have become the implementation carriers of modern high-level electronic design methods.
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